The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement of a method for forming a connection hole in an interlayer insulation film to establish contact with a lower layer wiring.
In a semiconductor device, such as a semiconductor integrated circuit, an interlayer insulation film is applied to a lower layer wiring, which includes the gate, drain, and source of a transistor. A connection hole is formed in the interlayer insulation film. Metal is charged in the connection hole to establish contact between the lower layer wiring and an upper layer wiring.
The connection hole is normally formed by performing anisotropic etching, which guarantees a selective ratio relative to the lower layer wiring, on the interlayer insulation film. It is known that excessive etching, or over-etching, of the interlayer insulation film occurs due to differences between lower layer wirings or interlayer insulation films. A connection hole may not be connected with the lower layer wiring due to insufficient etching of the interlayer insulation film even if another connection hole is connected with the lower layer wiring. Therefore, over-etching is performed so that each connection hole is connected with the lower layer wiring.
However, over-etching may be performed on the region adjacent to the lower layer wiring. This may subsequently cause electric connection between unexpected regions and the lower layer wiring when metal is charged in the connection hole. More specifically, misalignment of the lower layer wiring and the connection hole or differences in the pattern size of the lower layer wiring may cause the connection hole to overhang from the lower layer wiring. When the connection hole overhangs from the lower layer wiring, regions adjacent to the lower layer wiring are also etched when over-etching is performed. Accordingly, when metal is charged on the etched region, which is adjacent to the connection hole, the lower layer wiring is electrically connected to unnecessary portions. This may affect the operation of the semiconductor integrated circuit.
Therefore, during the designing of a semiconductor device in the prior art, the size of the lower layer wiring and the arrangement of the connection hole are provided with allowances taking into consideration misalignment of the lower layer wiring and the connection hole. The allowances for the size of the lower layer wiring and the arrangement of the connection hole avoid the above problem. However, this enlarges the area of the lower layer wiring and consequently decreases the integration of the semiconductor integrated circuit.